The present invention relates in general to multilevel logic circuits and in particular to an improved multilevel logic circuit utilizing a voltage clamp to minimize voltage changes on floating nodes.
A multilevel transistor logic circuit selectively connects a current source to a voltage source through a load resistor and a series of switches so that current from the current source passes through the load resistor only if all of the switches are closed. A commonly employed two-level logic circuit comprises an emitter-coupled npn transistor pair having collectors coupled through load resistors to a voltage source and emitters selectively connected to a current source through a switch. An input signal is applied to the base of a first transistor of the pair and a reference signal is applied to the base of the second transistor of the pair. A clock signal controls switch operation. When, for example, the clock signal is high, the switch is closed and the input signal is at high logic level, an output voltage signal appearing between the collectors of the first and second transistors is negative. When the input signal swings low the output voltage swings positive. When the clock signal goes low, the switch opens, both transistors turn off and the output signal is unaffected by the input signal.
Such a logic circuit is useful, for example, as a buffer stage for a latch circuit having a regenerative latching output stage that operates when the clock signal goes low, the output signal produced by the buffer stage being applied as input to the latching output stage. When the clock signal is high, the polarity of the buffer stage output signal is determined by the magnitude of its input signal. When the clock signal goes low, the output stage latches the output of the buffer to its current state as of the falling edge of the clock signal.
In some applications it is desirable that a latch hold its state for a long time and then respond quickly to a short clock pulse that closes the switch only briefly. During the time that the clock signal is low, the switch is open and the emitters of the transistor pair of the buffer stage constitute a "floating node" that is no longer coupled to the voltage source because both transistors of the emitter-coupled pair are off. However, leakage current through the transistor pair charges inherent circuit capacitance at the node and eventually causes the voltage of the floating node to rise up to the source voltage. When the clock signal goes high again so as to close the switch, the current source must remove built-up charge from this inherent circuit capacitance before the voltage of the floating node can be reduced to a level sufficient to permit the first or second transistor to turn on. Thus, in order for the latch output to properly respond to the input signal, the clock signal must remain high to keep the switch closed for a minimum amount of time to allow for discharge of capacitance at the floating node, and that minimum amount of time increases with the duration of the low portion of the clock signal.